Programmable resistance memory element and method for making same

ABSTRACT

A programmable resistance memory element. The active volume of memory material is made small by the presence of a small area of contact between the conductive material and the memory material. The area of contact is created by forming a region of conductive material and an intersecting sidewall layer of the memory material. The region of conductive material is preferably a sidewall layer of conductive material.

RELATED APPLICATION INFORMATION

[0001] This application is a continuation-in-part of U.S. patentapplication Ser. No. 09/276,273 filed on Mar. 25, 1999 which is acontinuation-in-part of U.S. patent application Ser. No. 08/942,000,filed on Oct. 1, 1999 and now abandoned. U.S. patent application Ser.No. 09/276,273 is hereby incorporated by reference herein.

FIELD OF THE INVENTION

[0002] The present invention relates to memory elements and, moreparticularly, to programmable resistance memory elements.

BACKGROUND OF THE INVENTION

[0003] Memory elements formed from materials that can be programmed toexhibit at least two detectably distinct electrical resistivities areknown in the art. One type of material that can be used as material forthese programmable elements is phase-change material. Phase-changematerials may be programmed between a first structural phase where thematerial is generally more amorphous and a second structural phase wherethe material is generally more crystalline. The term amorphous, as usedherein, refers to a condition that is relatively structurally lessordered or more disordered than a single crystal and has a detectablecharacteristic, such as high electrical resistivity. The termcrystalline as used herein, refers to a condition that is relativelystructurally more ordered than amorphous and has lower electricalresistivity than the amorphous phase. Since programmable memory elementsmade with a phase-change material can be programmed to a high resistancestate or a low resistance state by changing the phase of the material,one phase can be used to store a logic 0 data bit, for example, whilethe other is used to store a logic 1 data bit.

[0004] The concept of utilizing phase-change materials for electronicmemory applications is disclosed, for example, in U.S. Pat. Nos.3,271,591 and 3,530,441. The early phase-change materials described inthe '591 and '441 patents were based on changes in local structuralorder. The changes in structural order were typically accompanied byatomic migration of certain species within the material. Such atomicmigration between the amorphous and crystalline phases made programmingenergies relatively high; the electrical energy required to produce adetectable change in resistance in these materials was typically in therange of about a microjoule. This amount of energy had to be deliveredto each individual memory element in a solid state matrix of rows andcolumns that made up a memory device. High energy requirementstranslated into high current carrying requirements for the address linesand for an isolation/address device associated with each discrete memoryelement in the memory device.

[0005] The high energy requirements needed to program the resistance ofthe memory elements described in the '591 and '441 patents limited theiruse as a direct and universal replacement for present computer memoryapplications, such as tape, floppy disks, magnetic or optical hard diskdrives, solid state disk flash, dynamic random access memory (DRAM),static random access memory (SRAM) and socket flash memory. For example,low programming energy is important when using a plurality ofprogrammable memory elements as electrically erasable programmableread-only memory (EEPROM), used for large-scale archival storage.Reducing the power consumption of mechanical hard drives (such asmagnetic or optical hard drives) by replacement with EEPROM hard drivesis of particular interest in such applications as lap-top computersbecause the mechanical hard disk drive is one of the largest powerconsumers therein. However, if the EEPROM replacement for hard driveshas high programming current requirements, and consequently high powerrequirements, the power savings may be inconsequential or, at best,unsubstantial. Thus, programmable memory elements, in order to be usedin memory devices capable of replacing a variety of conventional memory,require low programming energy.

[0006] The programming energy requirements of individual memory elementsmay be reduced in different ways. For example, the programming energymay be reduced by appropriate selection of the composition of the memorymaterial. An example of a phase-change material having reduced energyrequirements is described in U.S. Pat. No. 5,166,758, the disclosure ofwhich is incorporated herein by reference. Other examples of memorymaterials are provided in U.S. Pat. Nos. 5,296,716, 5,414,271,5,359,205, and 5,534,712, the disclosures of which are all incorporatedherein by reference.

[0007] It has been further found that the performance of devicesincorporating these memory elements are closely linked to the activevolume of the phase-change material that is being addressed. Thus, theprogramming energy requirement may also be reduced through appropriatemodification of the electrical connection whereby programming energy isdelivered to the memory material. For example, a reduction inprogramming energy may be achieved by modifying the composition or shapeof the electrical connection. Examples of such modifications areprovided in U.S. Pat. Nos. 5,341,328, 5,406,509, 5,534,711, 5,536,947,5,933,365 and RE37,259, the disclosures of which are all incorporatedherein by reference.

[0008] The memory elements are generally formed in integrated circuitsusing sequential wafer processing. However, optimal performance andminimal programming current, and thus minimal energy, are typicallyobtained at dimensions for the active volume of phase-change materialthat fall below the minimum printable lithographic dimension. That is,using standard wafer processing techniques where the area of contactbetween an electrode and the phase-change material arelithographically-defined, the area of contact, and thus the activevolume of phase-change material extending from that area of contact, maybe larger than desired. Modification of the electrical connection, whichtypically involves the addition of processing steps in the formation ofthe memory element designed to reduce the active volume, can becomplicated and add variability in the area of contact fromelement-to-element in a memory array including many such elements.

SUMMARY OF THE INVENTION

[0009] An aspect of the present invention is an improved programmableresistance memory element in which the energy requirements for theprogramming of the element may be reduced. This may be accomplished by aprogrammable memory element comprising a region of conductive materialembedded in a first region of dielectric material deposited upon asubstrate. The conductive material is adapted to receive an electricalinput signal from a signal source. The element also includes a sidewalllayer of memory material embedded in a second dielectric regiondeposited upon the first region, a bottom surface of the sidewall layerof memory material is in electrical communication with a top surface ofthe region of conductive material. The memory material is preferablyformed as a sidewall spacer of memory material. The top surface of theconductive material and the bottom surface of the memory materialpreferably form only one area of contact. The area of contact preferablyhas dimensions corresponding to a width of the top surface of theconductive material and a width of the bottom surface of the memorymaterial. The width of the top surface of the conductive material andthe width of the bottom surface of the memory material may each benon-lithographically defined.

[0010] Another aspect of the present invention is a programmable memoryelement, comprising: an electrode; and a sidewall layer of programmableresistance memory material having a bottom surface in electricalcommunication with the electrode. The sidewall layer of programmableresistance memory material is preferably a sidewall spacer ofprogrammable resistance material.

[0011] Another aspect of the present invention is a method of forming aprogrammable resistance memory element in such a way that theprogramming energy requirement for the element may be reduced. Themethod of forming the programmable memory element comprises the step ofembedding a region of conductive material in a first region ofdielectric material deposited upon a substrate, the conductive materialadapted to receive an electrical input signal from a signal source. Themethod further includes the step of embedding a sidewall layer of memorymaterial in a second dielectric region deposited upon the first region,a bottom surface of the sidewall layer of memory material in electricalcommunication with a top surface of the region of conductive material.The memory material is preferably in the form of a sidewall spacer ofmemory material. The top surface and the bottom surface preferably formonly one area of contact between the region of conductive material andthe sidewall layer of memory material, the area of contact preferablyhaving dimensions corresponding to a width of the top surface and awidth of the bottom surface.

[0012] Variations in the inventive memory element and method accordingto the present invention are contemplated and are described herein.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The various features, advantages and other uses of the inventionwill become more apparent by referring to the following detaileddescription and drawing in which like numbers refer to like elementsthroughout the several views and in which:

[0014]FIG. 1 is a high-level diagram of a memory device includingperiphery circuitry and a memory array incorporating programmableresistance memory elements according to the present invention;

[0015]FIG. 2 is a schematic diagram of a memory array according to FIG.1;

[0016]FIG. 3 is a schematic diagram of a memory cell incorporating amemory element and an isolation device;

[0017]FIG. 4 is a block diagram of a process for making a memory cellincorporating the programmable resistance memory element according toone embodiment of the present invention;

[0018]FIG. 5 is a simplified two-dimensional representation of thefabrication of an isolation device of the memory cell of FIG. 3;

[0019]FIGS. 6 through 19B are simplified two- and three-dimensionalrepresentations of the fabrication layers of memory elementsincorporating the isolation device of FIG. 5 and corresponding to steps50 through 78 of FIG. 4;

[0020]FIG. 20A is a plan view of a first embodiment of a memory elementshowing the contact area of the memory material and a first electrodeprior to the placement of a second electrode;

[0021]FIG. 20B is a plan view of a second embodiment of a memory elementshowing the contact area of the memory material and the first electrodeprior to the placement of the second electrode;

[0022]FIG. 21A is an alternative embodiment of FIG. 20A;

[0023]FIG. 21B is an alternative embodiment of FIG. 20B; and

[0024]FIGS. 22 through 23 are simplified two-dimensional representationsof the fabrication layers of memory elements incorporating the isolationdevice of FIG. 5 and corresponding to steps 80 through 84 of FIG. 4.

DETAILED DESCRIPTION OF THE INVENTION

[0025] Programmable resistance memory elements comprise a volume ofphase-change memory material that is programmable between at least afirst resistance state and a second resistance state in response toprogramming electrical signals, such as currents, of differentamplitudes and durations. Memory material programmable to two resistancestates means that the associated memory element is capable of storing asingle bit of information, either a logic 0 or a logic 1, for example.In another embodiment, the memory material is programmable to at leastthree resistance states so that each of the memory elements is capableof storing more than one bit of information. For example, memorymaterial programmable to at least four resistance states makes a memoryelement capable of storing at least two bits of information. Each of theresistance states resulting from a programming electrical signal isassigned a value, such as logic 0 or logic 1 where two resistive statesexist. Another electrical signal, a read electrical signal, applied tothe memory element may be used to read the resistance of the memorymaterial, thus indicating the value stored by the memory element.

[0026] The memory element also includes means for delivering theseelectrical signals from a signal source to the volume of memorymaterial. As described herein, the electrical signals for each memoryelement are supplied by one or more electrical connections, referred toas electrodes herein. Although it is preferred, the electrodes do nothave to be in physical contact with the memory material as discussed inmore detail herein; they merely need to be in electrical communicationwith the memory material. Additional details regarding the programmingand reading of the memory elements are included in, for example, U.S.Pat. Nos. 5,912,839 and 6,075,719, each of which is incorporated hereinby reference.

[0027] Turning now to the drawings, and referring initially to FIG. 1,individual programmable resistance memory elements (shown in FIG. 2) canbe combined into a memory array, or matrix, 14 in a memory device 10.The memory device 10 includes a plurality of memory cells 20 for storingdata. The memory matrix 14 is an integrated circuit memory array 14 andis coupled to periphery circuitry 16 by a plurality of control lines 18.The periphery circuitry 16 includes circuitry for addressing the memorycells 20 contained within the memory and may include circuitry forstoring data in and retrieving data from the memory cells 20. Theperiphery circuitry 16 may also include other circuitry used forcontrolling or otherwise ensuring the proper functioning of the memorydevice 10. The memory matrix 14 and the periphery circuitry 16 of thememory device 10 are shown on a common semiconductor substrate 100, butthis is not necessary. The matrix 14 and circuitry 16 could each be oneor more separate integrated circuits coupled on one or more circuitboards with appropriate interconnections.

[0028] A schematic diagram of the memory array 14 is shown in FIG. 2. Ascan be seen, the memory array 14 includes a plurality of memory cells 20arranged in generally perpendicular rows and columns. The memory cells20 in each row are coupled together by a respective wordline 22, and thememory cells 20 in each column are coupled together by a respectivebitline 24. More specifically, each memory cell 20 includes a wordlinenode 26 that is coupled to a respective wordline 22, and each memorycell 20 includes a bitline node 28 that is coupled to a respectivebitline 24. The conductive wordlines 22 and bitlines 24 are electricallycoupled to the periphery circuitry 16 (shown in FIG. 1) through thecontrol lines 18 so that each of the memory cells 20 can be accessed forthe storage and retrieval of information.

[0029]FIG. 3 illustrates an exemplary memory cell 20 that may be used inthe memory array 14. The memory cell 20 includes a memory element 30coupled to an address device 32 that electrically isolates each memoryelement 30 from all other memory elements 30 in the array 14. Theaddress devices 32 thus permit each discrete memory cell 20 to be readand written to without interfering with information stored in adjacentor remote memory cells 20 of the array 14. While the address device 32is shown as a diode 32 in FIG. 3, the memory cells 20 may incorporateany type of isolation/addressing device. For example, a transistor, suchas a bipolar junction transistor and any type of field-effect transistor(FET) including a junction FET (JFET) and a metal oxide semiconductorFET (MOSFET), can be used in place of the diode 32. The memory element30 is a programmable resistive element that can be made of a chalcogenand other materials, as will be more fully explained below. Asillustrated in FIG. 3, the memory element 30 is coupled to a wordline 22at a wordline node 26, and the diode 32 is coupled to a bitline 24 at abitline node 28. However, it should be understood that these connectionsof the memory cell 20 may be reversed without adversely affecting itsoperation or the operation of the memory array 14.

[0030] The process steps associated with making a memory cell 20according to FIG. 3 are shown in FIG. 4 starting at step 50, with stepsillustrated with reference to FIGS. 5-23, which are not drawn to scale.The memory cell 20 is preferably formed upon a single crystal siliconsemiconductor wafer, or substrate, 100 incorporating the address devices32, the conductive wordlines 22 and bitlines 24 and the memory elements30. It is efficient to fabricate the address devices 32 and the memoryelements 30 on the same substrate 100 in the manner described. One ofskill in the art will recognize from the description herein, however,that other arrangements of the address devices 32 and the memoryelements 30 are possible. For example, the address devices 32 may befabricated on a separate section of the substrate 100 from the memoryelements 30 with electrical communications provided between thesections. This description also, as mentioned, assumes that the addressdevice is a diode 32. Use of another address device 32 requires changesin the fabrication layers herein described, which changes are within thelevel of skill of one in the art.

[0031] In step 50, the isolation/address device, the diode 32, is formedin a multi-step process. The cross-sectional view of a partial result ofthe process is shown in FIG. 5. The wafer substrate is first p-doped toform a p-substrate 100. Formed in the p-substrate 100 by diffusion in amanner well known in the art are n+ channels forming the conductivebitlines 24 extending across the chip in a direction perpendicular tothe plane of the illustration, i.e., in the y direction. On top of thisn+ grid is formed an n-doped crystalline epitaxial layer 110, which maybe about 5,000 Angstroms thick, by example. Using known masking anddoping techniques, p-doped isolation channels 112 are formed in then-epitaxial layer 110. These p-doped isolation channels 112 extend allthe way down into the p-substrate 100 and extend completely around andisolate and define islands 114 of the n-epitaxial layer 110. Instead ofp-doped isolation channels, silicon dioxide (SiO₂) isolation trenchescan be used for isolation of the islands 114 according to knowntechniques.

[0032] A layer 116 of thermally grown SiO₂ is then deposited over thisstructure. Etching, again according to known techniques, forms apertures118 in the layer 116 over the islands 114. Diffusion regions 120 of p+material are formed within the areas defined by the apertures 118. Thesemiconductor junctions of the p+ regions 120 and the n-epitaxial layer110 form p-n junction diodes 32 in series with each of the regions ofthe n-epitaxial layer exposed through the apertures 118 of the SiO₂layer 116.

[0033] A contact 122 to each diode 32 is next formed in the aperture 118in step 54, again according to known techniques. Alternatively, as oneof skill in the art will realize from the description herein, thecontacts 122 can be self-aligned after step 56. It should be noted thatalthough a plurality of contacts 122 are shown formed in the apertures118 used to form the diffused p+ regions 120, this is not necessary.First, in certain embodiments, the contact 122 may be omitted as thefirst electrode 134, described herein, can perform the series contactwith the p+ region 120. Alternatively, each contact 122 is in aconductive path with the p+ region 120, but extends laterally, i.e., inthe x direction, from a region adjacent the p+ region 120 to a regioncorresponding to at least a portion of an adjoining isolation channel112. The contact 122 can also be one continuous contact 122 coupled toan insulation layer (not shown). The contact(s) 122 can be a silicidesuch as titanium silicide, cobalt silicide or tungsten silicide, but cancomprise other materials according to desired barrier and conductiveproperties. Suitable materials for the contact(s) 122 any insulationlayer(s), are discussed in detail in U.S. Pat. Nos. 5,933,364 andRE37,259.

[0034] Starting at step 56, the memory elements 30 are deposited overrespective contacts 122, if included, or otherwise in individual ohmicelectrical series contact with the p+ regions 120 the diodes 32 tocreate memory cells 20. To simplify the drawing figures, the remainderof the steps will show the configuration of FIG. 5 upon which oneexemplary memory element 30 is deposited as reference number 124. Itshould be understood that while the fabrication of only a single memorycell 20 is discussed, a plurality of similar memory cells 20 aretypically fabricated simultaneously. Although not illustrated in thisone element 30 example, each memory element 30 is electrically isolatedfrom other memory elements 30 in any suitable manner, such as by theaddition of embedded field oxide regions, so that each memory cell 20 ofthe array 14 is electrically isolated.

[0035] In step 56, a photo and etch process is performed to create a viaor trench 128 in a dielectric layer, preferably an oxide layer. First,and as shown with reference to FIG. 6, a layer of dielectric material126 is formed on top of the substrate base 124. The dielectric layer 126is any suitable dielectric material and is preferably a first oxidelayer, i.e., SiO₂, deposited by a known technique, such as by chemicalvapor deposition (CVD). In a top surface 126T of the first oxide layer126, an opening 128 is formed by a suitable method to the contact 122,or to the underlying p+ region 120 where the contact 122 is not used.The photo and etch process is a standard photolithographic techniquewhereby a photoresist is first spun onto the top of a surface, here thelayers of the substrate 100, at high speed to form a thin uniform layer.A positive photoresist, or resist, is a photo-sensitive chemical that,when exposed to light, can be dissolved and removed by resist developer.A mask, which contains a pattern of transparent and opaque areas, islaid over the chip, and the mask is exposed to light. The resist notexposed to light hardens and provides protection for the portions of thelayers under that resist. The exposed resist is removed and an etchaccording to any number of known methods can occur on the underlyinglayers. Then, the remaining resist is removed in preparation for thenext step. Although all of these steps are not discussed explicitlyherein with respect to the steps of the present invention, it isrecognized by one of skill in the art that photolithography is generallya part of the fabrication of each layer of a chip.

[0036] Here, using standard photolithographic techniques, a mask (notshown) may be deposited on top of the first oxide layer 126 with theappropriate pattern. The opening 128 may thus be sized at thephotolithographic limit, which is currently greater than 0.1 μm (1000Angstroms). The opening 128 may be any shape. In FIG. 6, the opening 128is shown as a via, i.e., a hole, in the insulating first oxide layer126. The via 128 is substantially circular, but may be rectangular, forexample. FIG. 7A is a simplified three-dimensional representation ofFIG. 6 where the opening is a via 128. Alternately, the opening may beformed as a shallow trench 128 as shown in FIG. 7B. The opening 128, inany case, includes a bottom surface 128B and at least one sidewallsurface 128S adjacent the periphery of the opening 128. The sidewallsurface 128S of the opening corresponds to the sidewall surface orsidewall surfaces of the oxide 126. Although the bottom surface 128B ismore clearly seen where the opening is a via 128, the bottom surface128B of a trench 128 is between two roughly parallel sidewall surfaces128S and adjacent the contact 122. As shown in the embodiments of theopenings of FIGS. 7A and 7B, the sidewall surface(s) 128S are preferablysubstantially vertically disposed (that is, they are preferablyperpendicular to the substrate).

[0037] The process next proceeds to step 58, where the first electrodematerial is deposited. Specifically, a conductive layer 130 is depositedonto the structure shown in either FIG. 7A or 7B. As illustrated in FIG.8, the conductive layer 130 is deposited on the top surface 126T of thefirst oxide layer 126, as well as on the sidewall surface 128S and onthe bottom surface 128B of the via 128. Hence, the layer 130 has a topportion 130T that is formed on the top surface 126T, a sidewall portion130S that is formed on the sidewall surface 128S and a bottom portion130B that is formed on the bottom surface 128B. Whatever form theopening 128 takes, the deposition of the layer 130 is preferably asubstantially conformal deposition. Hence, the top portion 130T of layer130 preferably conforms to the top surface 126T, the sidewall portion130S of layer 130 preferably conforms to the sidewall surface 128S, andthe bottom portion 130B preferably conform to the bottom surface 128B ofthe via 128. The thickness “t” of the conductive layer 130 is shown.

[0038] The conductive material used for the conductive layer 130 may beany conductive material and may include, but is not limited to, n-typedoped polysilicon, p-type doped polysilicon, p-type doped silicon carbonalloys and/or compounds, n-type doped silicon carbon alloys and/orcompounds, titanium-tungsten, tungsten, tungsten silicide, molybdenumand titanium nitride. Other examples include titanium carbon-nitride,titanium aluminum-nitride, titanium silicon-nitride and carbon.

[0039] A portion of the conductive layer 130 forms the first, or bottomelectrode in contact with the memory material 150 (not shown in FIG. 8)of the memory element 30. Forming a suitable contact region for thefirst electrode starts when the conductive layer 130 is etched in theprocess at step 60. If the opening is a trench 128, a directional spaceretch is preferably performed, which etch is preferably selective to thefirst oxide layer 126 and the contact 122. This anisotropic etch ispreferably a dry etch, i.e., it is carried out by a reactive gas. Thedry etch can be a plasma etch, a reactive ion etch or a magneticallyenhanced reactive ion etch, for example. A plasma etch uses a gas suchas hydrogen bromide or chlorine. The result of this step is to removesubstantially all portions of the conductive layer 130 that are parallelto the substrate (that is, that are horizontal) and leave substantiallyall portions which are perpendicular to substrate (that is, that arevertical). Hence, the anisotropic etch removes substantially all of thehorizontally disposed top layer portion 130T and substantially all ofthe horizontally disposed bottom layer portion 130B. The etch leavessubstantially all of the sidewall layer portion 130S that was formed onthe sidewall surface 128S. Referring to FIG. 9B, the result of theanisotropic etch is to leave a sidewall layer 134 of conductivematerial. In the embodiment shown, the sidewall layer 134 of conductivematerial is a sidewall spacer of conductive material.

[0040] If the opening is a via 128, an angular etch of a select portionof the conductive layer 130 is also possible. Of course, such an etchmay also remove a portion of the first oxide layer 126. The angular etchcan be performed by, for example, ion milling directed at a 45 or 60degree angle to the plane of the substrate 100. The appearance of theconductive layer 130 after this step is shown in FIG. 9A. Alternatively,and although not shown in the process steps, a conventional photo andetch step can be performed after step 64 but prior to step 66, asdiscussed herein.

[0041] In step 62, a conformal dielectric layer 132 is again depositedby a known technique, such as by CVD. This dielectric layer 132, likethe first oxide layer 126, can be any suitable dielectric material, butis preferably SiO₂ and is thus referred to herein as the second oxidelayer 132. This conformal second oxide layer 132 is shown in FIG. 10 forthe embodiment where the opening is a via 128. In step 64, dry etchingor chemical mechanical planarization (CMP) is used to planarize the topsurface of the structure of FIG. 10, or a corresponding structure wherethe opening is a trench 128, to expose an embedded conductive layer 134.Of course, when using CMP an etch stop is sometimes useful. An etch stopis a layer of material of a character that slows the etch process, butdoes not necessarily stop the etch. It provides a means for indicatingwhen the etch is nearing completion. Here, such a stop can be optionallydeposited on the top surface 126T of the oxide layer 126 during step 56.During the planarization in step 64, the stop, when detected, can beremoved by known means, such as dry etching, and a minimal re-polish canoccur after the removal. In either case, the structure of FIG. 10 afterthis planarization step is shown in FIG. 11.

[0042] In the embodiment shown in FIG. 11, the resulting embeddedconductive layer 134 (which is the bottom electrode of the memoryelement) includes a portion which is a sidewall layer 130S formed on thesidewall surface of the oxide 126. The conductive layer 134 alsoincludes an additional component. In the embodiment shown in FIG. 11,the additional component is a substantially horizontally disposed bottomlayer 130B. (It is noted that the conductive layer 134 may be formed ona bottom surface and a sidewall surface of an opening, such as a hole ortrench, so as to form a conductive liner).

[0043] Hence, in the embodiments shown FIGS. 9B and 11, the bottomelectrode of the memory element (which is the conductive layer 134 shownin FIGS. 9B and 11) includes a sidewall layer of conductive materialformed on a sidewall surface. The bottom electrode may also include anadditional component, such as the horizontally disposed bottom layer ofconductive material 130B.

[0044] As noted, the conductive layer 134 forms a bottom electrode forthe memory element. Also, as noted above, in the embodiments ofinvention shown in FIGS. 9B and 11, the conductive layer 134 includes asidewall layer of conductive material. More generally, the bottomelectrode may take any form and have any structure. The conductive layer134 is more generically referred to as a conductive region 134 herein.This is to clarify that the conductive region 134, may have any shapeand is not limited to the shapes shown in the embodiments of FIGS. 9Band 11. Hence, it is possible, that the bottom electrode may take anyform or shape (and it does not have to include a conductive sidewalllayer).

[0045] Preferably, the portion of the top surface 134T of the conductiveregion 134 exposed to the memory material layer 150, described herein,has a dimension less than the photolithographic limit. Using the exampleof the embodiments shown in FIGS. 9B and 11, this dimension is a widthW1. The width W1 is preferably less than about 1000 Angstroms, morepreferably less than about 500 Angstroms, and most preferably less thanabout 300 Angstroms.

[0046] In the embodiments shown in FIGS. 9B and 11, the width W1 of thetop surface 134T of the sidewall layer 134 is defined by the thicknessof the conformal deposition of the conductive layer 130 shown in FIG. 8.This width W1 is preferably smaller than that achievable by standardphotolithography. More specifically, the width W1 is preferably lessthan the photolithographic limit. As discussed, the photolithographiclimit is currently greater than approximately 0.1 μm (1000 Angstroms).In other embodiments, one where the top surface 134T is shaped as anannulus (or a portion of an annulus), for example, the width W1 could bethe difference between the inner and outer diameters of the annulus.Possible values for the width WI will be discussed in more detailherein.

[0047]FIG. 12A is a top view of the structure of FIG. 10 showing theexposed top surface 134T of the conductive region 134 and the first andsecond oxide layers 126 and 132. Similarly, a top view of the structureof FIG. 9B after performing steps 62 and 64 is shown in FIG. 12B.Although a bottom portion 130B of the conductive layer 130 in is shownin FIGS. 12A and 12B for clarity, the figures make it clear that thesecond oxide layer 132 covers whatever remains of the bottom portion130B, since most of the bottom portion 130B can be removed. It is alsoclear in FIG. 12B that the section of the sidewall portion 130S notperpendicular to the plane of the figure is also covered by the secondoxide layer 132 in this view. Thus, in FIG. 12A the only portion of theconductive region 134 exposed through the dielectric region formed bythe remaining portions of the first and second oxide layers 126 and 132is a semicircular top surface 134T of a sidewall layer of width W1.Similarly, in FIG. 12B, the only portion of the conductive region 134exposed through the dielectric region formed by the remaining portionsof the first and second oxide layers 126 and 132 is a straight topsurface of a sidewall layer having a width W1.

[0048] The cross-sectional views of FIGS. 5, 6, 8, 9A, 10 and 11 areshown in the direction indicated along line 136-136 in FIG. 12A, whilethe cross-sectional view of FIG. 9B is shown in the direction indicatedalong line 138-138 in FIG. 12B. For the discussion of the next steps ofFIG. 4, the cross-sectional views in the directions indicated by line140-140 of FIG. 12A and line 142-142 of FIG. 12B are used. These viewsare shown in FIGS. 13A and 13B, respectively.

[0049] In step 66 of FIG. 4, a thin, conformal dielectric layer 144 isdeposited by known techniques, such and physical or chemical vapordeposition. Although a nitride, i.e., silicon nitride Si₃N₄, ispreferred, an insulator with a similar dielectric constant and goodbarrier properties can also be used. To distinguish this dielectriclayer 144 from the other layers, it is referred to herein as the nitridelayer 144. In step 68, another dielectric layer 146 is conformallydeposited, again according to known methods. Although like the first andsecond oxide layers 126, 132, layer 146 typically comprises SiO₂,another excellent insulator material can be used. If SiO₂ is used in anyor all of the layers 126, 132, 146, its source is preferably tetraethylorthosilicate (TeOS). The structure of FIG. 13A including these layersis shown in FIG. 14. The dielectric layer 146 is referred to as thethird oxide layer 146 herein to distinguish it from the remainder of thelayers.

[0050] A photo and etch step is performed in step 70, which preferablyresults in a sidewall surface 148 shown in FIG. 15. The sidewall surface148 extends through the nitride layer 144 and the third oxide layer 146to contact the top surface 134T of the conductive region 134. It ispossible that the sidewall surface 148 may be formed as the sidewallsurface of an opening such as a trench or a hole (the hole may have acircular cross-section). In step 72, a layer 150 of memory material isdeposited over the top of the structure of FIG. 15. The memory materialcomprising the layer 150 may be any programmable resistance materialknown in the art. Preferably, the programmable resistance material is aphase-change material. Preferably, the phase-change material is capableof exhibiting a first order phase transition. For example, U.S. Pat. No.5,166,758 and other prior art patents describe a phase-change memorymaterial incorporating at least one chalcogen element. The chalcogenelement may be chosen from the group consisting of Te, Se and mixturesor alloys thereof. The memory material may further include at least oneelement selected from the group consisting of Ge, Sb, Bi, Pb, Sn, As, S,Si, P, O and mixtures or alloys thereof. In one embodiment, the memorymaterial comprises the elements Te, Ge and Sb. In another embodiment,the memory material consists essentially of Te, Ge and Sb. An example ofa memory material that may be used is Te₂Ge₂Sb₅.

[0051] The phase-change memory material of the layer 150 may alsoinclude at least one transition metal element. The term transition metalas used herein includes elements 21 to 30, 39 to 48, 57 and 72 to 80.Preferably, the one or more transition metal elements are selected fromthe group consisting of Cr, Fe, Ni, Nb, Pd, Pt and mixtures or alloysthereof. The memory materials that include transition metals may beelementally modified forms of the memory materials in the Te—Ge—Sbternary system. This elemental modification may be achieved by theincorporation of transition metals into the basic Te—Ge—Sb ternarysystem, with or without an additional chalcogen element, such as Se.

[0052] A first example of an elementally modified memory material is aphase-change memory material including Te, Ge, Sb and a transition metalin the ratio: (Te_(a)Ge_(b)Sb_(100−(a+b)))_(c)TM_(100−c); wherein thesubscripts a, b and c are in atomic percentages totaling 100% of theconstituent elements; TM is one or more transition metals, preferablyincluding Cr, Fe, Ni, Nb, Pd, Pt and mixtures or alloys thereof; a and bare as set forth for the basic Te—Ge—Sb ternary system; and c is betweenabout 90% and about 99.99%.

[0053] A second example of an elementally modified memory material is aphase-change memory material including Te, Ge, Sb, Se and a transitionmetal in the ratio:(Te_(a)Ge_(b)Sb_(100−(a+b)))_(c)TM_(d)Se_(100−(c+d)); wherein thesubscripts a, b, c and d are in atomic percentages totaling 100% of theconstituent elements; TM is one or more transition metals, preferablyincluding Cr, Fe, Ni, Nb, Pd, Pt and mixtures or alloys thereof; a and bare as set forth for the basic Te—Ge—Sb ternary system; c is betweenabout 90% and 99.5%; and d is between about 0.01% and 10%. Other detailsof suitable memory materials are described in U.S. Pat. No. 5,933,365.

[0054] As mentioned, the memory material layer 150 is deposited in step72 over the top of the structure shown in FIG. 15. It is preferable thatthe deposition of the memory material layer 150 be a substantiallyconformal deposition in step 72. The phase-change memory materialdiscussed herein can be sputter deposited while in the substantiallyamorphous state, but the ability to deposit a conformal layer may belimited by the aspect ratio, i.e., the height of the sidewall surface148 compared to the width of the top surface 132T of the second oxidelayer 132 and the portion of the top surface 134T of the conductiveregion 134 to be covered. If necessary, the substrate 100 and its layerscan be tilted during the deposition in step 72 to improve the profile ofthe conformal memory material layer 150. Other known techniquestypically used for deposition would not generally result in a conforminglayer 150. Adjusting the shape of the memory material layer 150 afterdeposit may be possible by such techniques as reflow and extrusion.

[0055] A conformal memory material layer 150 is shown in FIG. 16. As itis substantially conforming, the layer 150 has a top surface 150Troughly conforming to the top of the second oxide layer 132, the portionof the top surface 134T of the conductive region 134 that is not coveredby the nitride layer 144, and the third oxide layer 146 and the topsurface 146T of the third oxide layer 146. Thus, the memory materiallayer 150 has a sidewall surface 150S roughly conforming to the sidewallsurface 148.

[0056] In step 74, a directional anisotropic spacer etch of the memorymaterial layer 150 is performed. Based upon the properties of thephase-change material and the shape of the memory material layer 150,ion milling may be the preferred technique of performing the spaceretch. The structure shown in FIG. 17 is the structure of FIG. 16 afterthe anisotropic spacer etch of step 74. The anisotropic etch removessubstantially all of the horizontally disposed components of the memorymaterial 150. The etch leaves a sidewall layer 151 of memory material onthe sidewall surface 148. The sidewall layer of memory material 151 hastop surface 15IT coincident with the top surface 146T of the third oxidelayer 146, a bottom surface 151B adjacent to a portion of the topsurface 134T of the conductive region 134, and two sidewall surfaces150S, one adjacent the sidewall surface 148 and the other opposed. Inthe embodiment shown the memory material sidewall layer 151 is asidewall spacer of memory material. It is possible that a memorymaterial sidewall spacer be formed on a sidewall surface of an openingsuch as a trench or a hole. If the sidewall spacer is formed on asidewall surface of a trench, then the bottom surface of the sidewallspacer would be a linear strip. If the sidewall spacer is formed on thesidewall surface of a hole with a substantially round cross-section,then the bottom surface of the sidewall spacer would be in the shape ofan annulus.

[0057] In step 76, a conformal dielectric layer 152, preferably an oxidesuch as SiO₂, is deposited over the structure of FIG. 17. The dielectriclayer 152, as with the other conformal layers dielectric layers, can bedeposited using any known technique, such as CVD. To distinguish it fromthe other layers, the dielectric layer 152 is referred to herein as thefourth oxide layer 152. The resulting structure is shown in FIG. 18.

[0058] The structure of FIG. 18 is planarized, preferably by CMP, toexpose the memory material sidewall layer 151 in step 78. The memorymaterial sidewall layer 151 is embedded in a dielectric region formed ofthe remaining portions of the nitride layer 144, the third oxide layer146 and the fourth oxide layer 152. The resulting structure is shown inFIG. 19A for the embodiment of FIGS. 13A and 14-18 wherein the openingis a via 128. Where the opening is a trench 128, steps 66-78 performedon the structure of FIG. 13B results in the structure shown in FIG. 19B.As shown in FIGS. 19A and 19B, the memory material sidewall layer 151has a width W2, which is defined by the thickness of the conformaldeposition of the memory material layer 150 shown in FIG. 16. Inparticular, the bottom surface 151B of the memory material sidewalllayer 151 has a width W2 which is defined by the thickness of theconformal deposition of the memory material layer 150 shown in FIG. 16.Like the width W1 of the exposed top surface 134T of the conductiveregion 134, the width W2 of the bottom surface 151 B of the memorymaterial sidewall layer 151 is preferably smaller than that achievableby standard photolithography. More specifically, the width W2 ispreferably less than the photolithographic limit, which is currentlygreater than approximately 0.1 μm (1000 Angstroms), as previouslymentioned. The width W2, like the width W1, will be discussed in moredetail herein.

[0059]FIG. 20A shows a top view of the structure of FIG. 19A, and FIG.20B shows a top view of the structure of FIG. 19B. In each of FIGS. 20Aand 20B, the top surface 134T of the conductive region 134 is shown withhidden lines so that both the conductive region 134 and the memorymaterial sidewall layer 151 are shown. The top surface 134T of theconductive region 134 and the bottom surface 151B of the memory materialsidewall layer 151 are formed so that they essentially lie in planesthat overlap in an area of contact A. Substantially all electricalcommunication between the conductive region 134 and the memory materialsidewall layer 151 occurs through this area of contact A. The area ofcontact A has dimensions that correspond to the widths W1 and W2. Thatis, the area A is roughly four-sided with a dimension in the x-directionof about width W1 and with a dimension in the y-direction of about widthW2.

[0060] It is noted that in the embodiment shown in FIGS. 20A and 20B,the width W1 is shown to extend in the x-direction while the width W2extends in the y-direction. In other embodiments, the width W1 and thewidth W2 may each extend in directions which are simply non-parallel(i.e. traverse) to each other. Preferably, the width W1 and the width W2extend in directions which are substantially perpendicular to eachother.

[0061] It is worth noting that width W1 and width W2 are typically notuniform over the entire area of contact A, and that when it is said thatthe area of contact A has dimensions that correspond to the widths W1and W2, it means that the area of contact A is roughly equal to W1 timesW2. Variations in surfaces created in the fabrication process, such asvariations in the sidewall surface 128S upon which the conductivematerial 130 is layered or variations in the sidewall surface 148 uponwhich the memory material 150 is layered, can affect the widths W1 andW2, respectively, over the area A. Indeed, these variations can effectthe widths W1 and W2 along the entire length of the top surface 134T andthe bottom surface 151B. Surface variations can result from unevenetching, for example. Similarly, variations in the conformal layer ofconductive material 130 or memory material 150 formed on the respectivesidewall surfaces 128S and 148 can also result in non-uniformity of thewidths W1 and W2. The variations that result in the non-uniformity inthe widths W1 and W2 can result in an area of contact A that does nothave four sides, but instead is only substantially four-sided with, forexample, rounded edges.

[0062] Further, even if the widths W1 and W2 were uniform along theentire length of the top surface 134T of conductive region 134 and thebottom surface 151B of the memory material sidewall layer 151,respectively, the widths W1 and W2 may not be uniform over the area A.This occurs when either of the surfaces 134T, 151B are not straightsidewall layers created by a trench or sidewall etch as previouslydescribed. Directing attention to FIG. 11, for example, when the openingis a via 128, the portion of the top surface 134T contacting the memorymaterial sidewall layer 151 is in the shape of a semicircular wedge.While the width W1 is the width of the wedge between its inner and outerdiameters, i.e., the width between the sidewall surface 128S and thesidewall surface 130S, it is clear that the width W1 is not uniform overthe entire area A. However, the area of contact A shown in FIGS. 20A-21Bcan be said to have dimensions corresponding to W1 and W2 and can beapproximated by W1 multiplied by W2. Here, the width W1 is preferablyless than about 1000 Angstroms, is more preferably less than about 500Angstroms and is, most preferably, less than about 300 Angstroms. Also,the width W2 is preferably less than about 1000 Angstroms, is morepreferably less than about 500 Angstroms and is, most preferably, lessthan about 300 Angstroms. The area of contact A is preferably less thanabout 1,000,000 square Angstroms, is more preferably less than about250,000 square Angstroms and is, most preferably, less than about 90,000square Angstroms.

[0063] It is noted that in the embodiments shown in FIGS. 20A and 20B,the bottom surface 151B of the memory material sidewall layer 151 is inthe form of a narrow strip extending across the length of the singlecell 20 structure. However, in the spacer etch step of the process,i.e., step 74, an additional etch of the memory material layer 150 mayoccur whereby at least a portion of the memory material layer 150 isremoved and filled with the fourth oxide layer 152 in step 76. Thisresults in the memory material sidewall layer 151 extending only aportion of length of the structure shown in FIGS. 20A and 20B.Additional etching can, in fact, result in the memory material layer 150forming a sidewall layer 151 as small as a hole or a pore. This isparticularly useful in the alternate embodiments of FIGS. 20A and 20Brespectively shown as FIG. 21A and 21B.

[0064]FIGS. 21A and 21B result from certain changes to the process stepsof FIG. 4. Specifically, if the etch of step 60 is skipped, the entireconductive layer 130 shown in FIG. 8 remains throughout the subsequentprocessing steps. This results in two contact areas of the memorymaterial sidewall layer 151 to the conductive region 134. Since a goalof the simplified process described herein is to minimize the contactarea between these two materials, this would be an undesirable result.As seen in FIGS. 21A and 21B, removal of portions of the memory materiallayer 150 when forming the sidewall layer 151 of memory material alsoresults in one small contact area A as previously described. After theadditional etch(es) in step 74, the fourth oxide layer 152 is depositedin step 76 as previously described, the CMP step 76 similarly occurs asdescribed.

[0065] Regardless of whether this variation in the process occurs ornot, steps 80-84 of FIG. 4 can take place. Deposited on top of thestructure resulting from steps 50-78 is a second conductive layer 156forming a second electrode. FIG. 22 shows a cross-section of thestructure of FIG. 20A in the direction indicated along the line 154-154after the deposit of the second conductive layer 156 in step 80. Thissecond conductive layer 156 can comprise the same material as the firstconductive layer 130 and be deposited according to the techniquespreviously discussed. In step 82, a standard photo and etch step of thesecond electrode 156 results in a plurality of conductive wordlines 22,which extend perpendicular in direction to the conductive bitlines 24shown in FIG. 5. One of the wordlines 22 formed from the secondelectrode 156 is shown in FIG. 23. The simplified process ends at step84.

[0066] While the second electrode 156 forms the conductive wordlines 22in the embodiment shown, this is not necessary. The second electrode 156can be formed of a contact material, such as that used for the contactlayer 122, shown in FIG. 5, with or without an insulation layer. Then,the conductive wordlines 22 can be formed of, for example, aluminumconductors 22 extending perpendicular in direction to the bitlines 24.In this description, the wafer 100 incorporates the conductive bitlines24 as the diodes 32 are connected to the conductive bitlines 24.However, if the connections of the diode 32 and the memory element 30were to be reversed, the wafer 100 would incorporate the conductivewordlines 22 and the second electrode 156 could form the conductivebitlines 24 in the manner described.

[0067] Although not shown, a top encapsulating layer of a suitableencapsulant such as Si₃N₄ or a plastic material such aspolyimide/polyamide is typically added to the cell 20 to seal thestructure against moisture and other external elements that could causedeterioration and degradation of performance. The encapsulant can bedeposited, for example, using a low temperature plasma depositionprocess. The polyimide/polyamide material can be spin deposited andbaked after deposition in accordance with known techniques to form theencapsulant layer. Also, although it is not shown in the exemplarysingle cell 20, when the cell 20 is incorporated in an array 14, thecontrol lines 18 to a signal supply, such as the periphery circuitry 16,are typically included in the layout on the substrate 100 according toknown techniques to contact wordlines 22 and bitlines 24.

[0068] The description herein is directed to the memory cell 20 shown inFIG. 3, which includes an inventive memory element 30 and an addressdevice 32 associated with each memory element 30. The memory element 30can also be constructed separate from the address device 32 upon thesubstrate 100 given the teachings herein and the level of skill in theart. The memory element 30 can be optionally combined with an addressdevice 32 formed upon the substrate 100 or another wafer to form amemory cell 20. The memory element 30 formed separate from an addressdevice 32 still include the conductive sidewall region 134 and thememory material sidewall layer 151 embedded in their dielectric regions.The memory element 30 would also include some type of first contact,such as contact 122, embedded in an insulating layer in the substrate100 and connectable to a signal supply. Preferably, the memory element30 would also include a second contact such as that formed from thesecond conductive layer 156. Then, both contacts are connectable to thesignal supply, such as a DC voltage supply (not shown).

[0069] Finally it is noted that additional layers may be included in thestructure described. For example, additional dielectric layers may beadded to optimize the processing and especially the etching stepsdescribed. Other layers may be added for insulation and barrierprotection. A particularly good example of the use of additional layersis the inclusion of barrier protection between the conductive region 134and the memory material sidewall layer 151. As mentioned at thebeginning of the description, an electrode of a memory element 30 neednot be in physical contact with the phase-change memory material;electrical communication is sufficient. A barrier layer of a suitablematerial can both improve the electrical communication between thesurfaces 134T and 151B and improve the physical connection between them.It this clear then, that the area of contact A as previously describedneed not be an area where the conductive region 134 and the memorymaterial sidewall layer 151 directly contact one another.

[0070] It is noted that electrode structures for programmable resistancememory elements are found in U.S. patent application Ser. Number09/276,273, the disclosure of which is incorporated by reference herein.

[0071] It is to be understood that the disclosure set forth herein ispresented in the form of detailed embodiments described for the purposeof making a full and complete disclosure of the present invention, andthat such details are not to be interpreted as limiting the true scopeof this invention as set forth and defined in the appended claims.

We claim:
 1. A programmable memory element, comprising: a region ofconductive material embedded in a first region of dielectric materialdeposited upon a substrate, the conductive material adapted to receivean electrical input signal from a signal source; and a sidewall layer ofprogrammable resistance memory material embedded in a second dielectricregion deposited upon the first region, a bottom surface of the sidewalllayer of memory material in electrical communication with a top surfaceof the region of conductive material.
 2. The memory element of claim 1,wherein said sidewall layer of memory material is a sidewall spacer ofmemory material.
 3. The programmable memory element of claim 1, whereinsaid region of conductive material is a sidewall layer of conductivematerial.
 4. The programmable memory element of claim 1, wherein saidregion of conductive material is a sidewall spacer of conductivematerial.
 5. The programmable memory element of claim 1, wherein saidregion of conductive material is a sidewall liner of conductivematerial.
 6. The programmable memory element of claim 1, wherein theregion of conductive material and the sidewall layer of memory materialhave an area of contact having dimensions corresponding to a width ofthe top surface of said region of conductive material and a width of thebottom surface of said sidewall layer of memory material.
 7. The memoryelement of claim 6, wherein the width of the top surface of the regionof conductive material is less than the photolithographic limit.
 8. Thememory element of claim 7, wherein the width of the top surface of theregion of conductive material is less than about 1000 Angstroms.
 9. Thememory element of claim 7, wherein the width of the top surface of theregion of conductive material is less than about 500 Angstroms.
 10. Thememory element of claim 7, wherein the width of the top surface of theregion of conductive material is less than about 300 Angstroms.
 11. Thememory element of claim 7, wherein the width of the bottom surface ofthe sidewall layer of memory material is less than the photolithographiclimit.
 12. The memory element of claim 7, wherein the width of thebottom surface of the sidewall layer of memory material is less thanabout 1000 Angstroms.
 13. The memory element of claim 3, wherein thewidth of the bottom surface of the sidewall layer of memory material isless than about 500 Angstroms.
 14. The memory element of claim 3,wherein the width of the bottom surface of the sidewall layer of memorymaterial is less than about 300 Angstroms.
 15. The memory element ofclaim 1, wherein said top surface and the bottom surface form only onearea of contact between the region of conductive material and thesidewall layer of memory material.
 16. The programmable memory elementaccording to claim 1 wherein the memory material is a phase-changematerial.
 17. The programmable memory element according to claim 16wherein the memory material comprises a chalcogen element.
 18. Aprogrammable memory element, comprising: an electrode; and a sidewalllayer of programmable resistance memory material having a bottom surfacein electrical communication with said electrode.
 19. The memory elementof claim 18, wherein said sidewall layer of programmable resistancematerial is a sidewall spacer of programmable resistance material. 20.The memory element of claim 18, wherein said electrode includes asidewall layer of a conductive material, the bottom surface of saidsidewall layer of memory material being in electrical communication witha top surface of said sidewall layer of conductive material.
 21. Thememory element of claim 18, wherein said electrode is a sidewall spacerof conductive material.
 22. The memory element of claim 18, wherein saidelectrode is a liner of conductive material.
 23. The memory element ofclaim 20, wherein the area of contact between said sidewall layer ofmemory material and said sidewall layer of conductive material isdefined by a width of the bottom surface of said sidewall layer ofmemory material and a width of a top surface of said sidewall layer ofconductive material.
 24. The memory element of claim 23, wherein thewidth of the top surface of said electrode has a sublithographicdimension.
 25. The memory element of claim 23, wherein the width of thetop surface of said electrode has a dimension less than 1000 Angstroms.26. The memory element of claim 23, wherein the width of the top surfaceof said electrode has a dimension less than 500 Angstroms.
 27. Thememory element of claim 23, wherein the width of the bottom surface ofsaid conductive spacer has a sublithographic dimension.
 28. The memoryelement of claim 23, wherein the width of the bottom surface of saidconductive spacer has a dimension less than 1000 Angstroms.
 29. Thememory element of claim 23, wherein the width of the bottom surface ofsaid conductive spacer has a dimension less than 500 Angstroms.
 30. Thememory element of claim 18, wherein said electrode and said programmableresistance material have only one area of contact.
 31. The memoryelement of claim 18, wherein said programmable resistance material is aphase-change material.
 32. The memory element of claim 18, wherein saidprogrammable resistance material includes a chalcogen element.
 33. Amethod of forming a programmable memory element, comprising the stepsof: embedding a region of conductive material in a first region ofdielectric material deposited upon a substrate, the conductive materialadapted to receive an electrical input signal from a signal source; andembedding a sidewall layer of memory material in a second dielectricregion deposited upon the first region, a bottom surface of the sidewalllayer of memory material in electrical communication with a top surfaceof the region of conductive material; and wherein the top surface andthe bottom surface form only one area of contact between the region ofconductive material and the sidewall layer of memory material, the areaof contact having dimensions corresponding to a width of the top surfaceand a width of the bottom surface.
 34. A programmable memory elementcreated by the method according to claim
 33. 35. The method according toclaim 33 wherein the step of embedding a region of conductive materialin a first region of dielectric material deposited upon a substratefurther comprises the steps of: depositing a first dielectric layer upona substrate, the first dielectric layer having a surface; forming anopening in the surface of the first dielectric layer, the opening havingat least one sidewall surface and a top surface; depositing a layer ofconductive material upon the surface of the first dielectric layer, theat least one sidewall surface and the top surface; removing portions ofthe layer of conductive material and the first dielectric layer to formthe region of conductive material; depositing a second dielectric layerupon the region of conductive material and any exposed remaining portionof the first dielectric layer; and removing portions of the seconddielectric layer to expose the top surface of the region of conductivematerial.
 36. The method according to claim 35 wherein the step ofembedding a sidewall layer of memory material in a second dielectricregion deposited upon the first region further comprises the steps of:depositing a third dielectric layer upon the top surface of the regionof conductive material and any exposed remaining portions of the firstdielectric layer and the second dielectric layer; forming at least onesidewall surface of the third dielectric layer by removing portions ofthe third dielectric layer to expose a portion of the top surface of theregion of conductive material, the at least one sidewall surface of thethird dielectric layer lying in a plane, the plane one of perpendicularto the at least one sidewall surface of the opening in the firstdielectric layer surface and parallel to a tangent of the at least onesidewall surface of the opening in the first dielectric layer surface;depositing a layer of memory material upon the exposed portion of thetop surface of the region of conductive material and any exposedremaining portions of the first dielectric layer and the seconddielectric layer and the third dielectric layer; and removing portionsof the memory material layer to form the sidewall layer of memorymaterial.
 37. The method according to claim 36, further comprising thesteps of: depositing a fourth dielectric layer upon the sidewall layerof memory material and upon any exposed portions of the first dielectriclayer and the second dielectric layer and the third dielectric layer;and removing portions of the fourth dielectric layer to expose a topsurface of the sidewall layer of memory material.
 38. The methodaccording to claim 37 wherein the step of depositing the fourthdielectric layer further comprises the step of depositing a conformalfourth dielectric layer using one of physical and chemical vapordeposition.
 39. The method according to claim 37 wherein the step ofremoving portions of the fourth dielectric layer further comprises thestep of performing a chemical mechanical planarization.
 40. The methodaccording to claim 37, further comprising the step of: depositing anelectrode in contact with the top surface of the sidewall layer ofmemory material.
 41. The method according to claim 36 wherein the stepof depositing the third dielectric layer further comprises the step ofdepositing a conformal third dielectric layer using one of physical andchemical vapor deposition.
 42. The method according to claim 36 whereinthe step of removing portions of the fourth dielectric layer furthercomprises the step of performing a chemical mechanical planarization.43. The method according to claim 36 wherein the step of forming atleast one sidewall surface of the third dielectric layer furthercomprises removing portions of the third dielectric layer using ananisotropic etch.
 44. The method according to claim 36 wherein the stepof depositing a layer of memory material further comprises the step ofdepositing a conformal layer of memory material.
 45. The methodaccording to claim 36 wherein the step of depositing a third dielectriclayer further comprises the steps of: depositing a nitride layer uponthe top surface of the region of conductive material and any exposedremaining portions of the first dielectric layer and the seconddielectric layer; and depositing an oxide layer upon the nitride layer.46. The method according to claim 35 wherein the step of forming theopening further comprises the step of one of: forming a via to aconductive element upon a surface of the substrate; and forming a trenchto the conductive element upon the surface of the substrate.
 47. Themethod according to claim 35 wherein the step of depositing the layer ofconductive material further comprises the step of depositing a conformallayer of conductive material by physical vapor deposition.
 48. Themethod according to claim 35 wherein the step of removing portions ofthe layer of conductive material and the first dielectric layer furthercomprises the step of: performing at least one of a directional spaceretch and an angular etch.
 49. The method according to claim 35 whereinthe step of depositing the second dielectric layer further comprises thestep of depositing a conformal layer of dielectric material by one ofphysical and chemical vapor deposition.
 50. The method according toclaim 35 wherein the step of removing portions of the second dielectriclayer further comprises the step of performing a chemical mechanicalplanarization.
 51. The method according to claim 35 wherein the step ofremoving portions of the layer of conductive material and the firstdielectric layer comprises the step of performing an anisotropic etch.52. The method according to claim 33, further comprising the step of:depositing a second electrode upon the sidewall layer of memorymaterial.
 53. The method according to claim 33, further comprising thestep of: forming an isolation device upon the substrate, the isolationdevice adapted to receive the electrical input from the signal source,and the isolation device in electrical communication with the region ofconductive material.
 54. The method according to claim 53 wherein theisolation device is a diode.
 55. The method according to claim 53,further comprising the step of: depositing an electrode in contact witha top of the sidewall layer of memory material.
 56. The method accordingto claim 53, further comprising the step of: forming a contact betweenthe isolation device and the region of conductive material.
 57. Themethod according to claim 33 wherein the width of the top surface of theregion of conductive material is less than the photolithographic limit.58. The method according to claim 33 wherein the width of the bottomsurface of the sidewall layer of memory material is less than thephotolithographic limit.
 59. The method according to claim 33 whereinthe width of the bottom surface of the sidewall layer of memory materialis less than the photolithographic limit.
 60. The method according toclaim 33 wherein the width of the top surface of the regon of conductivematerial is less than about 500 Angstroms.
 61. The method according toclaim 33 wherein the width of the bottom surface of the sidewall layerof memory material is less than about 500 Angstroms.
 62. The methodaccording to claim 33 wherein the width of the bottom surface of thesidewall layer of memory material is less than about 500 Angstroms. 63.The method according to claim 33, further comprising the step of:forming the region of conductive material in a cup shape wherein the topsurface is formed by a circular sidewall layer, the width of which isdefined by the difference between an outer circumference and an innercircumference of the circular sidewall layer.
 64. The method accordingto claim 33 wherein the memory material is a phase-change materialcomprising a chalcogen element.
 65. The method according to claim 33,further comprising the steps of: forming an isolation device upon thesubstrate, the isolation device adapted to receive the electrical inputfrom the signal source, and the isolation device in electricalcommunication with the region of conductive material; depositing anelectrode in contact with a top surface of the sidewall layer of memorymaterial; and electrically connecting one of a conductive wordline and aconductive bitline to the isolation device and the other of theconductive wordline and the conductive bitline one of being theelectrode and electrically connected to the electrode; and wherein theconductive wordline and the conductive bitline are connectable in anarray including a plurality of like programmable memory elements andisolation devices.
 66. The method according to claim 33 wherein the topsurface is formed by a straight sidewall layer.
 67. The method accordingto claim 33 wherein the top surface is formed by a semicircular sidewalllayer.